1. Technical Field of the Invention
The present invention relates to an image rejection mixer, and a receiver using the mixer.
2. Description of the Prior Art
Conventionally, many of receivers such as radio communication devices have an image rejection mixer for removing an image signal component out of a received radio frequency signal. Hereafter, the conventional image rejection mixer will be described by referring to the drawing.
FIG. 6 is a block diagram of an image rejection mixer device described in JP 10-190359 A (1998). FIG. 7 is an equivalent circuit diagram of phase shifters of the image rejection mixer device shown in FIG. 6. The phase shifters include CR lattice circuits each having capacitors C and resistors R.
As for local oscillator signals to be applied to two mixers 101 and 102 in the image rejection mixer device shown in FIG. 6, a signal supplied from a common local oscillation source is shifted in phase by +45° and −45° by using, for example, phase shifters 103 and 104, respectively, resulting in a quadrature phase state.
Thereafter, I and Q output signals, respectively, of the mixers 101 and 102 are further shifted in phase by 90° with respect to each other by, for example, a+45° for phase shifter 105 and a−45° for phase shifter 10, respectively. Resulting I and Q output signals are added in an adder circuit 107. As a result, signal components of “requested” sidebands obtained from these two output signals reinforce each other. On the other hand, signal components of “image” sidebands cancel each other.
Furthermore, as shown in FIG. 7, emitter-coupled transistor pair 125 and 126 are supplied with I and Q channel signals having opposite phases, respectively. Current signals supplied from collector electrodes of the transistors 125 and 126 are shifted in phase by +45° and −45° by phase shifter means 127 and 128, respectively. Resultant signals are added at an output terminal 133 connected to collector electrodes of transistors 129 and 132 and an output terminal 134 connected to collector electrodes of transistors 130 and 131.
The transistors 129 and 130 are connected to paired transistors 125 in a cascode form, respectively. Furthermore, the transistors 131 and 132 are connected to paired transistors 126 in a cascode form, respectively. A bias potential is supplied to base electrodes of the transistors 129 to 132 through a common path 135. For each of the emitter-coupled transistor pair 125 and 126, only one current source 136 is required. Only two current sources in total are thus required. Therefore, the current taken out from a power supply which is not illustrated can be suppressed down to the minimum.
In the conventional technique, a CR lattice circuit is used in each phase shifter. Since the CR lattice circuit is current-driven by a constant current source, however, power dissipation becomes high. The reason will be described now. It is desired that values of capacitors C1 and C2 and resistors R1 and R2 of the CR lattice circuit are determined so as to satisfy the following equations,C1R1=(1−cos α)/2πf sin αC2R2=(1+sin α)/2πf cos αwhere f is the IF operation frequency. In the case where the IF operation frequency is large, it dissipation becomes high.
Furthermore, in the conventional technique, each phase shifter includes a transistor pair and a current source. The transistor pair and the current source may cause noise and distortion. If noise or the like occurs, the noise figure of the image rejection mixer becomes large and the reception sensitivity becomes worse in some cases. Reduction of noise and distortion is therefore demanded.
For making the input impedance of an adder used in the conventional technique small so as to be close to 0, it is necessary to input a greater DC current to the adder. If it is attempted to input a greater DC current, however, the power dissipation in the image rejection mixer becomes higher.